A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.