Invention Grant
- Patent Title: Semiconductor module including first and second wiring portions separated from each other
- Patent Title (中): 半导体模块包括彼此分离的第一和第二布线部分
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Application No.: US13558523Application Date: 2012-07-26
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Publication No.: US09087831B2Publication Date: 2015-07-21
- Inventor: Isao Ozawa
- Applicant: Isao Ozawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-167697 20110729
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/498 ; H01L23/00 ; H01L25/065 ; H01L23/31 ; H01L21/56
Abstract:
According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire.
Public/Granted literature
- US20130187272A1 SEMICONDUCTOR MODULE Public/Granted day:2013-07-25
Information query
IPC分类:
