Invention Grant
- Patent Title: Method for wafer level packaging and a package structure thereof
- Patent Title (中): 晶圆级封装方法及其封装结构
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Application No.: US14198493Application Date: 2014-03-05
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Publication No.: US09087912B2Publication Date: 2015-07-21
- Inventor: Tsung Jen Liao
- Applicant: CHIPMOS TECHNOLOGIES INC
- Applicant Address: TW Hsinchu
- Assignee: CHIPMOS TECHNOLOGIES INC.
- Current Assignee: CHIPMOS TECHNOLOGIES INC.
- Current Assignee Address: TW Hsinchu
- Agent Chun-Ming Shih
- Priority: TW102131200A 20130830
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00

Abstract:
The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.
Public/Granted literature
- US20150061121A1 METHOD FOR WAFER LEVEL PACKAGING AND A PACKAGE STRUCTURE THEREOF Public/Granted day:2015-03-05
Information query
IPC分类: