A pre-emphasis circuit is disclosed. In one embodiment, a pre-emphasis circuit includes a first signal path configured to receive a first signal and a second signal path configured to receive the first signal. The second signal path includes a re-timing circuit configured to delay the first signal by a pre-determined amount to produce a second signal. The pre-emphasis circuit also includes a summing circuit coupled to receive the first signal from the first signal path and the second signal from the second signal path. The summing circuit is configured to add the second signal to the first signal to produce a third signal, wherein the third signal is logically equivalent to the first signal. The third signal has a first magnitude for a first portion of a bit-time of the first signal, and a second magnitude for a second portion of the bit-time of the first signal.