A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.