Invention Grant
- Patent Title: Semiconductor devices with output circuit and pad
- Patent Title (中): 具有输出电路和焊盘的半导体器件
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Application No.: US14591817Application Date: 2015-01-07
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Publication No.: US09093283B2Publication Date: 2015-07-28
- Inventor: Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Kawasaki-shi
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2005-345347 20051130
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L23/00 ; H01L27/092 ; H01L23/528
Abstract:
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
Public/Granted literature
- US20150108579A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-04-23
Information query
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