Invention Grant
US09096032B2 Wafer processing laminate, wafer processing member, temporary bonding arrangement, and thin wafer manufacturing method
有权
晶片加工层压板，晶片加工部件，临时粘接装置和薄晶片制造方法
- Patent Title: Wafer processing laminate, wafer processing member, temporary bonding arrangement, and thin wafer manufacturing method
- Patent Title (中): 晶片加工层压板，晶片加工部件，临时粘接装置和薄晶片制造方法
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Application No.: US13868503Application Date: 2013-04-23
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Publication No.: US09096032B2Publication Date: 2015-08-04
- Inventor: Hideto Kato , Michihiro Sugo , Shohei Tagami , Hiroyuki Yasuda
- Applicant: SHIN-ETSU CHEMICAL CO., LTD.
- Applicant Address: JP Tokyo
- Assignee: SHIN-ETSU CHEMICAL CO., LTD.
- Current Assignee: SHIN-ETSU CHEMICAL CO., LTD.
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2012-098734 20120424
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/48 ; B32B7/06 ; H01L21/02 ; B32B7/12 ; H01L21/762 ; H01L23/00 ; H01L21/683 ; C09J7/02
Abstract:
A wafer processing laminate is provided comprising a support (3), a temporary adhesive layer (2), and a wafer (1). The temporary adhesive layer (2) has a trilayer structure consisting of a first temporary bond layer (A) of thermoplastic siloxane bond-free polymer, a second temporary bond layer (B) of thermoplastic siloxane polymer, and a third temporary bond layer (C) of thermosetting modified siloxane polymer. In a peripheral region, the second layer (B) is removed so that the first layer (A) is in close contact with the third layer (C).
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