Invention Grant
- Patent Title: III-V photonic integration on silicon
- Patent Title (中): 硅片上的III-V光子集成
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Application No.: US14501783Application Date: 2014-09-30
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Publication No.: US09097848B2Publication Date: 2015-08-04
- Inventor: John E. Bowers
- Applicant: The Regents of the University of California
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agency: Kaplan Breyer Schwarz & Ottesen, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; G02B6/122 ; H01L31/18 ; H01S5/02 ; H01S5/026 ; H01S5/125 ; G02B6/12 ; G02F1/017 ; H01S5/343 ; H01L27/146 ; H01L31/12 ; H01S5/183

Abstract:
Photonic integrated circuits on silicon are disclosed. By bonding a wafer of HI-V material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. The coupling between the silicon waveguide and the III-V gain region allows for integration of low threshold lasers, tunable lasers, and other photonic integrated circuits with Complimentary Metal Oxide Semiconductor (CMOS) integrated circuits.
Public/Granted literature
- US20150055911A1 III-V Photonic Integration on Silicon Public/Granted day:2015-02-26
Information query
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