A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight j of number B. The multiplier may include a first counter associated with the number A and may count modulo n and be paced by a clock. The multiplier may include a second counter associated with the number B and paced by the clock. Switching circuitry may produce the terms AiBj by taking the content of the first and second counters respectively as weights i and j. Shifting circuitry is configured to shift the content of one of the first and second counters when the other counter has achieved a revolution.