Invention Grant
- Patent Title: Double patterning layout design method
- Patent Title (中): 双图案布局设计方法
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Application No.: US14258065Application Date: 2014-04-22
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Publication No.: US09098670B2Publication Date: 2015-08-04
- Inventor: Tae-Joong Song , Jae-Ho Park , Kwang-Ok Jeong
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2013-0072507 20130624
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F7/00 ; G03F1/70

Abstract:
A double patterning layout design method includes defining critical paths including a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout includes anchoring the critical paths on the schematic circuit.
Public/Granted literature
- US20140380256A1 DOUBLE PATTERNING LAYOUT DESIGN METHOD Public/Granted day:2014-12-25
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