Invention Grant
- Patent Title: Semiconductor device manufacturing method
- Patent Title (中): 半导体器件制造方法
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Application No.: US13958685Application Date: 2013-08-05
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Publication No.: US09099349B2Publication Date: 2015-08-04
- Inventor: Naoyuki Kofuji , Nobuyuki Negishi , Hiroaki Ishimura
- Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
- Applicant Address: JP Tokyo
- Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
- Current Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2012-280480 20121225
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/115 ; H01L29/66 ; H01L29/792 ; H01L21/311

Abstract:
In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
Public/Granted literature
- US20140175534A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2014-06-26
Information query
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