Invention Grant
- Patent Title: Process for fabricating an enhancement mode heterojunction transistor
- Patent Title (中): 用于制造增强型异质结晶体管的工艺
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Application No.: US14090173Application Date: 2013-11-26
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Publication No.: US09099491B2Publication Date: 2015-08-04
- Inventor: Matthew Charles
- Applicant: Commissariat a l'energie atomique et aux energies alternatives
- Applicant Address: FR Paris
- Assignee: Commissariat a l'energie atomique et aux energies alternatives
- Current Assignee: Commissariat a l'energie atomique et aux energies alternatives
- Current Assignee Address: FR Paris
- Agency: Occhiuti & Rohlicek LLP
- Priority: FR1261208 20121126
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/778 ; H01L29/10 ; H01L29/20

Abstract:
A method for fabricating a heterojunction field-effect transistor includes implanting p-type dopants form an implanted area in a first layer of III-V semiconductor alloy, removing an upper part of the first layer and of the implanted area by maintaining vapor phase epitaxy conditions, stopping the removal when the density of the dopant at the upper face of the implanted area is maximal, forming a second layer of III-V semiconductor alloy by vapor phase epitaxy on the implanted area and on the first layer, forming a third layer of III-V semiconductor alloy by vapor phase epitaxy in order to form an electron gas layer at the interface between the third layer and the second layer, and forming a control gate on the third layer plumb with the implanted area.
Public/Granted literature
- US20140147977A1 PROCESS FOR FABRICATING AN ENHANCEMENT MODE HETEROJUNCTION TRANSISTOR Public/Granted day:2014-05-29
Information query
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