Invention Grant
US09099496B2 Method of forming an active area with floating gate negative offset profile in FG NAND memory
有权
在FG NAND存储器中形成具有浮动栅负偏移分布的有源区的方法
- Patent Title: Method of forming an active area with floating gate negative offset profile in FG NAND memory
- Patent Title (中): 在FG NAND存储器中形成具有浮动栅负偏移分布的有源区的方法
-
Application No.: US14472611Application Date: 2014-08-29
-
Publication No.: US09099496B2Publication Date: 2015-08-04
- Inventor: Ming Tian , Jayavel Pachamuthu , Atsushi Suyama , James Kai , Raghuveer S. Makala , Yao-Sheng Lee , Johann Alsmeier , Henry Chien , Masanori Terahara , Hirofumi Watatani
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES INC.
- Current Assignee: SANDISK TECHNOLOGIES INC.
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/788 ; H01L29/792 ; H01L27/115

Abstract:
A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.
Public/Granted literature
- US20140367762A1 METHOD OF FORMING AN ACTIVE AREA WITH FLOATING GATE NEGATIVE OFFSET PROFILE IN FG NAND MEMORY Public/Granted day:2014-12-18
Information query
IPC分类: