Invention Grant
- Patent Title: Testing process for semiconductor devices
- Patent Title (中): 半导体器件的测试过程
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Application No.: US13312758Application Date: 2011-12-06
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Publication No.: US09099547B2Publication Date: 2015-08-04
- Inventor: Stefan Martens , Mathias Vaupel
- Applicant: Stefan Martens , Mathias Vaupel
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/78 ; H01L21/66

Abstract:
In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.
Public/Granted literature
- US20130084659A1 Testing Process for Semiconductor Devices Public/Granted day:2013-04-04
Information query
IPC分类: