A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer.