Invention Grant
US09100052B2 QC-LDPC convolutional codes enabling low power trellis-based decoders
有权
QC-LDPC卷积码可实现低功率网格解码器
- Patent Title: QC-LDPC convolutional codes enabling low power trellis-based decoders
- Patent Title (中): QC-LDPC卷积码可实现低功率网格解码器
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Application No.: US14033229Application Date: 2013-09-20
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Publication No.: US09100052B2Publication Date: 2015-08-04
- Inventor: Eran Pisek
- Applicant: Eran Pisek
- Applicant Address: KR Suwon-Si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-Si
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/25 ; H03M13/03 ; H03M13/11 ; H03M13/41
Abstract:
A low-density parity check (LDPC) encoding method for increasing constraint length includes determining a LDPC code block H-matrix including a systematic submatrix (Hsys) of input systematic data and a parity check submatrix (Hpar) of parity check bits. The method includes diagonalizing the parity check submatrix (Hpar). The method includes identifying a set of rows of the H-matrix that form a complete set of the input systematic data. The method includes selecting an input bit granularity (γ) and encoding latency. The method further includes obtaining a quasi-cyclic LDPC (QC-LDPC) convolutional code H-Matrix. Further, the method includes combining the set of rows into a single row.
Public/Granted literature
- US20140223254A1 QC-LDPC CONVOLUTIONAL CODES ENABLING LOW POWER TRELLIS-BASED DECODERS Public/Granted day:2014-08-07
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