A memory controller and a method of calibrating the memory controller are provided. Input circuitry in the memory controller receives a differential pair of data strobe signals from a memory and generates a logical data strobe signal in dependence on a voltage difference between the differential pair of data strobe signals. Hysteresis circuitry, when active, increases by a predetermined offset a threshold voltage difference at which the input circuitry changes a logical state of the logical data strobe signal. Gate signal generation circuitry generates a data strobe gating signal, wherein the memory controller interprets the logical data strobe signal as valid when the data strobe gating signal is asserted. The memory controller performs a training process to determine a timing offset for the data strobe gating signal with respect to said logical data strobe signal, wherein the training process provides a first phase in which the hysteresis circuitry is active and a second phase in which the hysteresis circuitry is inactive.