Invention Grant
- Patent Title: Multi-level cells and method for using the same
- Patent Title (中): 多层细胞及其使用方法
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Application No.: US14229647Application Date: 2014-03-28
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Publication No.: US09105343B2Publication Date: 2015-08-11
- Inventor: Yuchen Zhou , Bing K Yen , Parviz Keshtbod , Mehdi Asnaashari
- Applicant: Avalanche Technology Inc.
- Applicant Address: US CA Fremont
- Assignee: Avalanche Technology, Inc.
- Current Assignee: Avalanche Technology, Inc.
- Current Assignee Address: US CA Fremont
- Agent Bing K. Yen
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C11/56

Abstract:
The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.
Public/Granted literature
- US20150131370A1 MULTI-LEVEL CELLS AND METHOD FOR USING THE SAME Public/Granted day:2015-05-14
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