Invention Grant
US09106227B2 Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
有权
在端子之间连接时，用于改善元件堆叠的电压处理和/或双向性的装置和方法
- Patent Title: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
- Patent Title (中): 在端子之间连接时，用于改善元件堆叠的电压处理和/或双向性的装置和方法
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Application No.: US14178116Application Date: 2014-02-11
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Publication No.: US09106227B2Publication Date: 2015-08-11
- Inventor: Tero Tapio Ranta , Shawn Bawell , Robert W. Greene , Christopher N. Brindle , Robert Mark Englekirk
- Applicant: PEREGRINE SEMICONDUCTOR CORPORATION
- Applicant Address: US CA San Diego
- Assignee: Peregrine Semiconductor Corporation
- Current Assignee: Peregrine Semiconductor Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Richman LLP
- Agent Martin J. Jaquez, Esq.; Alessandro Steinfl, Esq.
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H03K17/16 ; H03M1/10 ; H03M1/80
Abstract:
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
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