Transceiver circuitry may include a storage element that receives data signals from an external element, an alignment detector circuit, and a register. The storage element has a write clock terminal that receives a channel clock signal and a read clock terminal that receives another channel clock signal. The alignment detector circuit is adapted to generate an asserted ready signal when a predefined pattern is detected in the received data signals. The register receives an output signal from the storage element and outputs the output signal based on the asserted ready signal that is generated by the alignment detector circuit. The register may be clocked by the same channel clock signal that is received at the read clock terminal of the storage element.