Invention Grant
- Patent Title: Thermo/electrical conductor arrangement for multilayer printed circuit boards
- Patent Title (中): 多层印刷电路板的热电导体布置
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Application No.: US14122661Application Date: 2011-06-01
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Publication No.: US09107296B2Publication Date: 2015-08-11
- Inventor: Igor Perez-Uria , Per Ferm
- Applicant: Igor Perez-Uria , Per Ferm
- Applicant Address: SE Stockholm
- Assignee: Telefonaktiebolaget L M Ericsson (publ)
- Current Assignee: Telefonaktiebolaget L M Ericsson (publ)
- Current Assignee Address: SE Stockholm
- Agency: Nicholson de Vos Webster & Elliott, LLP
- International Application: PCT/SE2011/050680 WO 20110601
- International Announcement: WO2012/166028 WO 20121206
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H01F5/00 ; H05K3/40

Abstract:
The present invention relates to a thermo/electrical conductor arrangement for multilayer printed circuit boards (PCBs). Using vias for the transport of heat from the interior of the PCB and for conducting high currents between the conducting layers have limitations. Via platings are very thin and vias filled with solder is an unreliable method as there is always a risk that the vias are not properly filled during the soldering process. The present invention overcomes this by inserting a pin of a current conductive material (such as copper) into the via so that the pin is brought into galvanic contact with the conducting layers in the PCB and where at least one end of the pin is freely protruding from the PCB thereby allowing the pin to conduct heat from the interior of the PCB to the protruding end of the pin for external cooling.
Public/Granted literature
- US20140085034A1 THERMO/ELECTRICAL CONDUCTOR ARRANGEMENT FOR MULTILAYER PRINTED CIRCUIT BOARDS Public/Granted day:2014-03-27
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