A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.