Invention Grant
US09111949B2 Methods and apparatus of wafer level package for heterogeneous integration technology 有权
用于异构集成技术的晶圆级封装的方法和装置

Methods and apparatus of wafer level package for heterogeneous integration technology
Abstract:
Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.
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