Invention Grant
- Patent Title: Methods and apparatus of wafer level package for heterogeneous integration technology
- Patent Title (中): 用于异构集成技术的晶圆级封装的方法和装置
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Application No.: US13536549Application Date: 2012-06-28
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Publication No.: US09111949B2Publication Date: 2015-08-18
- Inventor: Chen-Hua Yu , Der-Chyang Yeh
- Applicant: Chen-Hua Yu , Der-Chyang Yeh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/60 ; H01L21/56 ; H01L23/00 ; H01L23/498 ; H01L23/538 ; H01L25/065 ; H01L25/16 ; H01L25/00 ; H01L23/31 ; H01L21/683 ; H01L23/64 ; H01L25/18

Abstract:
Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.
Public/Granted literature
- US20130264684A1 Methods and Apparatus of Wafer Level Package for Heterogeneous Integration Technology Public/Granted day:2013-10-10
Information query
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