Invention Grant
- Patent Title: Method for ensuring DPT compliance for auto-routed via layers
- Patent Title (中): 确保自动路由通过层DPT合规性的方法
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Application No.: US13622949Application Date: 2012-09-19
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Publication No.: US09112000B2Publication Date: 2015-08-18
- Inventor: James Walter Blatchford
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L21/768
Abstract:
A method of generating an integrated circuit with a double patterning technology (DPT) compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.
Public/Granted literature
- US20130072020A1 Method For Ensuring DPT Compliance for Auto-Routed Via Layers Public/Granted day:2013-03-21
Information query
