Invention Grant
US09118342B2 Low power excess loop delay compensation technique for delta-sigma modulators
有权
用于Δ-Σ调制器的低功率多余环路延迟补偿技术
- Patent Title: Low power excess loop delay compensation technique for delta-sigma modulators
- Patent Title (中): 用于Δ-Σ调制器的低功率多余环路延迟补偿技术
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Application No.: US14033047Application Date: 2013-09-20
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Publication No.: US09118342B2Publication Date: 2015-08-25
- Inventor: Vikas Singh , Anand Kannan , Ashish Lachhwani
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORTED
- Current Assignee: TEXAS INSTRUMENTS INCORPORTED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H03M3/00
- IPC: H03M3/00 ; H03M1/00 ; H03M1/46

Abstract:
A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.
Public/Granted literature
- US20150084797A1 LOW POWER EXCESS LOOP DELAY COMPENSATION TECHNIQUE FOR DELTA-SIGMA MODULATORS Public/Granted day:2015-03-26
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