Invention Grant
- Patent Title: Receiver circuit and receiving method
- Patent Title (中): 接收电路和接收方式
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Application No.: US14189840Application Date: 2014-02-25
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Publication No.: US09118451B2Publication Date: 2015-08-25
- Inventor: Masaya Kibune , Hirotaka Tamura
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox LLP
- Priority: JP2013-128527 20130619
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A receiver circuit includes: an input ADC configured to convert an input data signal to sample data in accordance with a clock; a boundary phase computation circuit configured to determine the boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to compute a maximum amplitude phase of an eye pattern of the input data signal based on the sample data and the boundary phase; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.
Public/Granted literature
- US20140376675A1 RECEIVER CIRCUIT AND RECEIVING METHOD Public/Granted day:2014-12-25
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