Invention Grant
- Patent Title: Semiconductor wafer test apparatus
- Patent Title (中): 半导体晶圆试验装置
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Application No.: US13148971Application Date: 2009-02-12
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Publication No.: US09121901B2Publication Date: 2015-09-01
- Inventor: Toshiyuki Kiyokawa , Takashi Naito
- Applicant: Toshiyuki Kiyokawa , Takashi Naito
- Applicant Address: JP Tokyo
- Assignee: ADVANTEST CORPORATION
- Current Assignee: ADVANTEST CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- International Application: PCT/JP2009/052302 WO 20090212
- International Announcement: WO2010/092672 WO 20100819
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/28 ; H01L21/683

Abstract:
An apparatus includes a plurality of test heads to which probe cards are electrically connected; a wafer tray which is able to hold a semiconductor wafer; and an alignment apparatus which positions the semiconductor wafer held on the wafer tray relatively with respect to the probe card so as to make the wafer tray face the probe card. The wafer tray has a pressure reducing mechanism which pulls the wafer tray toward the probe card. The alignment apparatus is configured to be able to move along the array direction of the test heads.
Public/Granted literature
- US20110316571A1 SEMICONDUCTOR WAFER TEST APPARATUS Public/Granted day:2011-12-29
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