Invention Grant
US09122617B2 Pseudo cache memory in a multi-core processor (MCP) 有权
多核处理器(MCP)中的伪缓存存储器

Pseudo cache memory in a multi-core processor (MCP)
Abstract:
Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches.
Public/Granted literature
Information query
Patent Agency Ranking
0/0