Invention Grant
US09122816B2 High performance system that includes reconfigurable protocol tables within an ASIC wherein a first protocol block implements an inter-ASIC communications protocol and a second block implements an intra-ASIC function
有权
包括ASIC内的可重配置协议表的高性能系统，其中第一协议块实现ASIC间通信协议，第二块实现ASIC内部功能
- Patent Title: High performance system that includes reconfigurable protocol tables within an ASIC wherein a first protocol block implements an inter-ASIC communications protocol and a second block implements an intra-ASIC function
- Patent Title (中): 包括ASIC内的可重配置协议表的高性能系统，其中第一协议块实现ASIC间通信协议，第二块实现ASIC内部功能
-
Application No.: US14542023Application Date: 2014-11-14
-
Publication No.: US09122816B2Publication Date: 2015-09-01
- Inventor: Thomas Edward McGee
- Applicant: Silicon Graphics International Corp.
- Applicant Address: US CA Milpitas
- Assignee: Silicon Graphics International Corp.
- Current Assignee: Silicon Graphics International Corp.
- Current Assignee Address: US CA Milpitas
- Agency: Sunstein Kann Murphy & Timbers LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/42
Abstract:
A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
Public/Granted literature
- US20150074375A1 Reconfigurable Protocol Tables Within An ASIC Public/Granted day:2015-03-12
Information query
