Invention Grant
- Patent Title: System-on-chip design structure and method
- Patent Title (中): 系统级芯片设计结构与方法
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Application No.: US13714771Application Date: 2012-12-14
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Publication No.: US09122824B2Publication Date: 2015-09-01
- Inventor: Mitsuru Tomono , Hiroaki Yoshida , Kodai Moritaka
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Maschoff Brennan
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F15/78

Abstract:
Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.
Public/Granted literature
- US20140173252A1 SYSTEM-ON-CHIP DESIGN STRUCTURE AND METHOD Public/Granted day:2014-06-19
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