Invention Grant
US09122832B2 Methods for controlling microloading variation in semiconductor wafer layout and fabrication
有权
用于控制半导体晶片布局和制造中的微加载变化的方法
- Patent Title: Methods for controlling microloading variation in semiconductor wafer layout and fabrication
- Patent Title (中): 用于控制半导体晶片布局和制造中的微加载变化的方法
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Application No.: US12512932Application Date: 2009-07-30
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Publication No.: US09122832B2Publication Date: 2015-09-01
- Inventor: Brian Reed , Michael C. Smayling , Scott T. Becker
- Applicant: Brian Reed , Michael C. Smayling , Scott T. Becker
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.
Public/Granted literature
- US20100031211A1 Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication Public/Granted day:2010-02-04
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