Invention Grant
- Patent Title: Adder
- Patent Title (中): 加法器
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Application No.: US14162812Application Date: 2014-01-24
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Publication No.: US09122896B2Publication Date: 2015-09-01
- Inventor: Tatsuya Ohnuki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2011-114035 20110520
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H03K17/00 ; G06G7/14 ; G06F1/32 ; G06F7/485

Abstract:
A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
Public/Granted literature
- US20140191791A1 ADDER Public/Granted day:2014-07-10
Information query
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