Invention Grant
US09123406B2 Semiconductor memory device capable of selectively enabling/disabling a first input unit and a second input unit in response to a first and second internal clock in a gear-down mode
有权
半导体存储器件能够响应于减速模式下的第一和第二内部时钟选择性地启用/禁用第一输入单元和第二输入单元
- Patent Title: Semiconductor memory device capable of selectively enabling/disabling a first input unit and a second input unit in response to a first and second internal clock in a gear-down mode
- Patent Title (中): 半导体存储器件能够响应于减速模式下的第一和第二内部时钟选择性地启用/禁用第一输入单元和第二输入单元
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Application No.: US14293649Application Date: 2014-06-02
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Publication No.: US09123406B2Publication Date: 2015-09-01
- Inventor: Yo-Sep Lee , Chang-Hyun Kim , Choung-Ki Song
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2013-0149724 20131204
- Main IPC: G11C8/18
- IPC: G11C8/18 ; G11C8/08 ; G11C8/06 ; G11C8/10
Abstract:
A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.
Public/Granted literature
- US20150155023A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2015-06-04
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