A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.