Invention Grant
- Patent Title: Layout method to minimize context effects and die area
- Patent Title (中): 布局方法，尽量减少上下文影响和模具面积
-
Application No.: US13622925Application Date: 2012-09-19
-
Publication No.: US09123562B2Publication Date: 2015-09-01
- Inventor: James Walter Blatchford , Thomas J. Aton
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/772 ; H01L21/8234 ; H01L27/02 ; H01L29/78
Abstract:
An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.
Public/Granted literature
- US20130069081A1 Layout Method To Minimize Context Effects and Die Area Public/Granted day:2013-03-21
Information query
IPC分类:
