Invention Grant
US09123569B1 Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator
有权
具有绝缘体III-V和硅锗晶体管的互补金属氧化物半导体结构
- Patent Title: Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator
- Patent Title (中): 具有绝缘体III-V和硅锗晶体管的互补金属氧化物半导体结构
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Application No.: US14199268Application Date: 2014-03-06
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Publication No.: US09123569B1Publication Date: 2015-09-01
- Inventor: Cheng-wei Cheng , Amlan Majumdar , Kuen-Ting Shiu
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Trentice V. Bolar; Louis J. Percello
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/84 ; H01L29/08 ; H01L27/12 ; H01L29/20

Abstract:
Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET.
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