Invention Grant
- Patent Title: Chip package and method for forming the same
- Patent Title (中): 芯片封装及其形成方法
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Application No.: US14529543Application Date: 2014-10-31
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Publication No.: US09123629B2Publication Date: 2015-09-01
- Inventor: Xiaochun Tan
- Applicant: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Applicant Address: CN Hangzhou
- Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
- Current Assignee Address: CN Hangzhou
- Agency: Westman, Champlin & Koehler, P.A.
- Priority: CN201310533175 20131031
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/00 ; H01L23/31

Abstract:
The present disclosure relates to a chip package and a method for forming the same. The chip package comprises a carrier pad, a chip, and a plurality of second conductive bumps, and a molding compound. The carrier pad has a first surface with a plurality of first conductive bumps formed thereon. The chip has an active surface. One end of each of the plurality of second conductive bumps is electrically coupled to the active surface, and the other end of each of the plurality of second conductive bumps is electrically coupled to the first conductive bumps. The molding compound encapsulates the chip and completely fills space between the carrier pad and the chip. In the chip package and the method for forming the same according to the present disclosure, the first conductive bumps are formed on the first surface of the carrier pad by etching, which provides an electrical connection between the first conductive bumps and the active surface of the chip, and broadens a flow channel of the molding compound between the chip and the carrier pad so that the molding compound can completely fill the space between the chip and the carrier pad. Underfill before encapsulation is not needed and the package cost is thus lowered.
Public/Granted literature
- US20150115439A1 CHIP PACKAGE AND METHOD FOR FORMING THE SAME Public/Granted day:2015-04-30
Information query
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