Method of forming drain extended MOS transistors for high voltage circuits

Invention Grant

US09123642B1 Method of forming drain extended MOS transistors for high voltage circuits 有权

Title translation: 形成用于高压电路的漏极扩展MOS晶体管的方法

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Patent Title: Method of forming drain extended MOS transistors for high voltage circuits
Patent Title (中): 形成用于高压电路的漏极扩展MOS晶体管的方法
Application No.: US14108967

Application Date: 2013-12-17
Publication No.: US09123642B1

Publication Date: 2015-09-01
Inventor: Sungkwon Lee , Igor Kouznetsov , Gyu-Chul Kim
Applicant: Cypress Semiconductor Corporation
Applicant Address: US CA San Jose
Assignee: Cypress Semiconductor Corporation
Current Assignee: Cypress Semiconductor Corporation
Current Assignee Address: US CA San Jose
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L21/266

Method of forming drain extended MOS transistors for high voltage circuits

Abstract:

A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

Abstract(Chinese):

提供了包括漏极扩展型半导体金属（DE_MOS）和低电压半导体（LV_MOS）晶体管及其制造方法的器件。在一个实施例中，该方法包括在衬底的DE_MOS区域中的第一DE_MOS晶体管的漏极部分中以第一能级注入第一类型的离子，以形成第一DE_MOS晶体管，并且注入第一类型的离子在衬底的LV_MOS区域中的第二能级调整第一LV_MOS晶体管的电压阈值，同时在第一DE_MOS晶体管的漏极部分中同时注入处于第二能级的第一类型的离子以形成漏极延伸的第一DE_MOS晶体管。还提供了其他实施例。

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺