Invention Grant
- Patent Title: Chip package structure and manufacturing method thereof
- Patent Title (中): 芯片封装结构及其制造方法
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Application No.: US14304975Application Date: 2014-06-15
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Publication No.: US09123684B2Publication Date: 2015-09-01
- Inventor: Tsung-Jen Liao
- Applicant: ChipMOS Technologies Inc.
- Applicant Address: TW Hsinchu
- Assignee: ChipMOS Technologies Inc.
- Current Assignee: ChipMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW102145621U 20131211
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/04 ; H01L23/10 ; H01L23/13 ; H01L23/14 ; H01L23/31 ; H01L23/495 ; H01L21/48 ; H01L23/00 ; H01L23/29 ; H01L23/367

Abstract:
A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.
Public/Granted literature
- US20150162260A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2015-06-11
Information query
IPC分类: