Invention Grant
- Patent Title: N/P boundary effect reduction for metal gate transistors
- Patent Title (中): 金属栅极晶体管的N / P边界效应降低
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Application No.: US14231809Application Date: 2014-04-01
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Publication No.: US09123694B2Publication Date: 2015-09-01
- Inventor: Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/423 ; H01L21/28 ; H01L29/66 ; H01L21/027 ; H01L21/8234 ; H01L21/3213 ; H01L27/02 ; H01L27/092 ; H01L29/49 ; H01L29/51

Abstract:
The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
Public/Granted literature
- US20140203374A1 N/P Boundary Effect Reduction for Metal Gate Transistors Public/Granted day:2014-07-24
Information query
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