Invention Grant
- Patent Title: Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
- Patent Title (中): 具有通过衬底通孔的集成电路结构和通过衬底通孔形成集成电路结构的方法
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Application No.: US13345422Application Date: 2012-01-06
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Publication No.: US09123700B2Publication Date: 2015-09-01
- Inventor: Jaspreet S. Gandhi , Brandon P. Wirz , Yangyang Sun , Josh D. Woodland
- Applicant: Jaspreet S. Gandhi , Brandon P. Wirz , Yangyang Sun , Josh D. Woodland
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L23/48 ; H01L23/00 ; H01L23/29 ; H01L21/56 ; H01L25/065
Abstract:
An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising opposing ends. A conductive bond pad is adjacent one of the ends on one side of the one substrate. A conductive solder mass is adjacent the other end projecting elevationally on the other side of the one substrate. Individual of the solder masses are bonded to a respective bond pad on an immediately adjacent substrate of the stack. Epoxy flux surrounds the individual solder masses. An epoxy material different in composition from the epoxy flux surrounds the epoxy flux on the individual solder masses. Methods of forming integrated circuit constructions are also disclosed.
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