Invention Grant
- Patent Title: Semiconductor constructions and methods of forming interconnects
- Patent Title (中): 半导体结构和形成互连的方法
-
Application No.: US14177030Application Date: 2014-02-10
-
Publication No.: US09123722B2Publication Date: 2015-09-01
- Inventor: Ming-Chuan Yang , Zengtao T. Liu , Vishal Sipani
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768

Abstract:
Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.
Public/Granted literature
- US20140151902A1 Semiconductor Constructions and Methods of Forming Interconnects Public/Granted day:2014-06-05
Information query
IPC分类: