Invention Grant
- Patent Title: Reduction of parasitic capacitance in a semiconductor device
- Patent Title (中): 降低半导体器件中的寄生电容
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Application No.: US13019695Application Date: 2011-02-02
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Publication No.: US09123807B2Publication Date: 2015-09-01
- Inventor: Akira Ito
- Applicant: Akira Ito
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L29/45 ; H01L29/49

Abstract:
An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.
Public/Granted literature
- US20120161233A1 Reduction of Parasitic Capacitance in a Semiconductor Device Public/Granted day:2012-06-28
Information query
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