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US09123807B2 Reduction of parasitic capacitance in a semiconductor device 有权
降低半导体器件中的寄生电容

Reduction of parasitic capacitance in a semiconductor device
Abstract:
An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.
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