Invention Grant
US09124416B2 Method for determining phase of clock used for reception of parallel data, receiving circuit, and electronic apparatus 有权
用于确定并行数据接收时钟的相位的方法,接收电路和电子设备

  • Patent Title: Method for determining phase of clock used for reception of parallel data, receiving circuit, and electronic apparatus
  • Patent Title (中): 用于确定并行数据接收时钟的相位的方法,接收电路和电子设备
  • Application No.: US14458780
    Application Date: 2014-08-13
  • Publication No.: US09124416B2
    Publication Date: 2015-09-01
  • Inventor: Ryoichi Inagawa
  • Applicant: FUJITSU SEMICONDUCTOR LIMITED
  • Applicant Address: JP Yokohama
  • Assignee: SOCIONEXT INC.
  • Current Assignee: SOCIONEXT INC.
  • Current Assignee Address: JP Yokohama
  • Agency: Arent Fox LLP
  • Priority: JP2013-188496 20130911
  • Main IPC: H03D3/24
  • IPC: H03D3/24 H04L7/033
Method for determining phase of clock used for reception of parallel data, receiving circuit, and electronic apparatus
Abstract:
For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.
Information query
Patent Agency Ranking
0/0