Invention Grant
- Patent Title: Computation of garbled tables in garbled circuit
- Patent Title (中): 在乱码电路中计算乱码表
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Application No.: US12660900Application Date: 2010-03-05
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Publication No.: US09124417B2Publication Date: 2015-09-01
- Inventor: Vladimir Y. Kolesnikov
- Applicant: Vladimir Y. Kolesnikov
- Applicant Address: FR Boulogne-Billancourt
- Assignee: Alcatel Lucent
- Current Assignee: Alcatel Lucent
- Current Assignee Address: FR Boulogne-Billancourt
- Agency: Patti & Malvone Law Group, LLC
- Main IPC: H04L9/06
- IPC: H04L9/06 ; H04L9/14 ; H04L9/28

Abstract:
An efficient encryption system for improving the computation speed of a garbled circuit is set forth. The garbled circuit includes a number of garbled Boolean gates having first and second garbled Boolean gate input wires. The system includes a first key ki on a first garbled gate input wire. A second key kj is also provided on a second garbled gate input wire. A programmable function is provided for combining the first key ki and the second key kj to obtain an encrypted output key. A method for expediting encryption and decryption of a garbled circuit having a number of encryptions for a garbled table of a garbled gate is also set forth. The method includes the steps of: forming the garbled table with a number of secret keys by applying a function to the secret keys to produce less than twice the number of secret keys as the number of encryptions for the garbled table, and evaluating the garbled table to decrypt an output key of the garbled table.
Public/Granted literature
- US20110216902A1 Computation of garbled tables in garbled circuit Public/Granted day:2011-09-08
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