According to one embodiment, a system includes a plurality of ports adapted for connecting to external devices and a switching processor. The switching processor includes a packet processor which includes a look-up interface, fetch and refresh logic (LIFRL) module and a packet processor logic (PPL) module adapted to operate in parallel, an internal look-up table cache including a plurality of look-up entries, each relating to a traffic flow which has been or is anticipated to be received by the switching processor, and a traffic manager module including a buffer memory which is connected to the plurality of ports. The LIFRL module is adapted for accessing the internal look-up table cache, the PPL module is adapted for communicating with the traffic manager module and the buffer memory, and the LIFRL module is adapted for communicating with one or more external look-up tables.