A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.