System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.