A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module.