Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to “store” the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the “stored” resultant gate-source voltage and the “stored” resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.